(Hong Kong)
Product Summary
The EPM7128STC100-10 of high-density, high-performance PLDs is based on second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7128STC100-10 provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. EPM7128STC100-10 in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.
Parametrics
EPM7128STC100-10 absolute maximum ratings: (1)VCC Supply voltage: -2.0 to 7.0 V; (2)VI DC input voltage: -2.0 to 7.0 V; (3)IOUT DC output current, per pin: -25 to 25 mA; (4)TSTG Storage temperature: -65 to 150 ℃; (5)TAMB Ambient temperature Under bias: -65 135 ℃; (6)TJ Junction temperature Ceramic packages, under bias: 150 ℃; (7)PQFP and RQFP packages, under bias: 135 ℃.
Features
EPM7128STC100-10 features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAXR architecture; (2)5.0-V in-system programmability (ISP) through the built-in; (3)IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices: ISP circuitry compatible with IEEE Std. 1532; (4)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (5)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (6)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (7)5-ns pin-to-pin logic delays with up to 175.4-MHz counter; (8)frequencies (including interconnect); (9)PCI-compliant devices available.
Diagrams
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 EPM7128STC100-10 |
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IC MAX 7000 CPLD 128 100-TQFP |
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EPM7128STC100-10F |
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IC MAX 7000 CPLD 128 100-TQFP |
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EPM7128STC100-10N |
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IC MAX 7000 CPLD 128 100-TQFP |
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